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74VHC393 Dual 4-Bit Binary Counter
March 1993 Revised March 1999
74VHC393 Dual 4-Bit Binary Counter
General Description
The VHC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains two independent counter circuits in one package, so that counting or frequency division of 8 binary bits can be achieved with one IC. This device changes state on the negative going transition of the CLOCK pulse. The counter can be reset to "0" (Q0-Q3 = "L") by a HIGH at the CLEAR input regardless of other inputs. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 170 MHz (typ) at TA = 25C s Low power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Pin and function compatible with 74HC393
Ordering Code:
Order Number 74VHC393M 74VHC393SJ 74VHC393MTC 74VHC393N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names CLR1, CLR2 CP1, CP2 QA, QB, QC, QD Description Clear Inputs Clock Pulse Inputs Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011571.prf
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74VHC393
Truth Table
Inputs CP X CLR H L L
X: Don't Care
Outputs QA L QB L QC L QD L
Count Up No Change
System Diagram
Timing Chart
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74VHC393
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 75 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 40.0 V A A IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND V V IOH = -4 mA IOH = -8 mA VIN = V IH IOL = 50 A or VIL V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = V IH IOH = -50 A or VIL Conditions
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74VHC393
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (CP -QA) tPLH tPHL Propagation Delay Time (CP -QB) tPLH tPHL Propagation Delay Time (CP -QC) tPLH tPHL Propagation Delay Time (CP -QD) tPLH tPHL Propagation Delay Time (CLR-Qn) fMAX Maximum Clock 5.0 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance
Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average operating current can be obtained by the equation: ICC(opr.) = CPD*VCC*fIN + ICC/2 (per Counter)
V CC (V) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3
TA = 25C Min Typ 8.6 11.1 5.8 7.3 10.2 12.7 6.8 8.3 11.7 14.2 7.7 9.2 13.0 15.5 8.5 10.0 7.9 10.4 5.4 6.9 75 45 125 85 120 65 170 115 4 23 10 Max 13.2 16.7 8.5 10.5 15.8 19.3 9.8 11.8 18.0 21.5 11.2 13.2 19.7 23.2 12.5 14.5 12.3 15.8 8.1 10.1
TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 65 35 105 75 10 Max 15.5 19.0 10.0 12.0 18.5 22.0 11.5 13.5 21.0 24.5 13.0 15.0 23.0 26.5 14.5 16.5 14.5 18.0 9.5 11.5
Units ns ns ns ns ns ns ns ns ns ns
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open (Note 3)
MHz
pF pF
AC Operating Requirements
Symbol tW(L) tW(H) tW(H) tREM Parameter Minimum Pulse Width (CP) Minimum Pulse Width (CLR) Minimum Removal Time VCC (V) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 TA = 25C Typ 5.0 5.0 5.0 5.0 5.0 4.0 T A = - 40C to +85C Guaranteed Minimum 5.0 5.0 5.0 5.0 5.0 4.0 Units
ns ns ns
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74VHC393
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74VHC393
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74VHC393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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